1. Field of the Invention
The invention generally relates to microelectronic devices, and more particularly to controlling the leakage current in complimentary metal oxide semiconductors (CMOS) integrated circuits.
2. Description of the Related Art
Leakage current occurs in a transistor as the gate' s performance declines in terms of its capability to control the flow of electric charge carriers in the channel between the source and drain of the device. Thus, even when the transistor is off, electric charge carriers continue to flow through the channel. In fact, a majority of the power consumed by an inactive transistor is a result of the leakage current.
Prior approaches in the field of leakage current control have suggested the use of active N-well and P-well biasing to adjunct individual chip threshold voltages (Vt) in order to tighten the leakage distribution and therefore improve yield as limited by the total power. With scaling, however, well biasing has become less effective and hence other approaches have been suggested, including using a double-gate CMOS having a second gate as a means of adjusting Vt. Unfortunately, the use of double-gate field effect transistors (FET) in the split-gate mode degrades their performance potential significantly due to the decreased drive with one gate and degraded sub-threshold turn-off behavior, requiring a higher Vt than the true double gate case.
FinFET devices have been used to reduce a transistor's leakage current by incorporating several gates rather than one to aid in controlling the flow of electric charge carriers in the device. Moreover, one solution to solve this problem is to use a dual gate structure with a n-type gate on one side of a channel and a p-type gate on the other, which aims to properly achieve the correct threshold voltage levels, which is the necessary gate voltage required to turn the transistor on (switch on).
Unfortunately, the leakage power, primarily due to sub-threshold channel currents, has become approximately equal to the switching power in high-performance integrated circuits. In fact, the leakage power varies, typically more than a decade, with the threshold voltage, Vt, variation driving the sub-threshold current variation. Therefore, there remains a need for a novel method and structure, which provides superior tuned leakage current control in a transistor device, such as a CMOS device.